Co-Design of Massively Parallel Embedded Processor Architectures

In this paper, we introduce a methodology for the systematic mapping, evaluation, and exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers. The investigated class of computer architectures can be described by massively parallel networked processing elements that, using today’s hardware technology, may be implemented on a single chip (SoC – System on a Chip). Existing approaches for mapping computational-intensive algorithms to parallel architectures either consider the implementation in dedicated hardware or the implementation on a given supercomputer. Many intermediate solutions between these extremes are coming up ranging from finegrained FPGAs to coarse-grained processor arrays. For these architectures, we propose in this contribution a codesign approach in the sense of designing special purpose parallel processor architectures and efficient mapping tools